1. Field of the Invention
The present invention relates to semiconductor circuit devices with signal line driving circuits and, more particularly, to a semiconductor circuit device including signal line driving circuits for transferring a signal between circuit blocks with low power, low-voltage-swing, and low current consumption at high speed.
2. Description of the Related Art
Due to higher-density integration, larger-scale integration and higher speed of recent semiconductor circuit devices, an increase of operating current and resultant generation have caused serious problem to occur in each semiconductor circuit device. An important challenge is to reduce the operating current. One approach to the challenge is to lower an external supply voltage or an internal reduced supply voltage supplied to a semiconductor circuit device, thereby reducing operating current. Unfortunately, when a supply voltage is merely lowered, the working speed of a circuit is lowered.
A general semiconductor circuit device includes circuit blocks and signal lines for transmitting signals between the circuit blocks. FIG. 10 shows an example (first related art) of a conventional general semiconductor circuit device fabricated by CMOS process. Each circuit block comprises a logic circuit 20 and a signal line driving circuit 25. The logic circuit 20 performs a logic operation on a signal supplied from an input signal line 1 and generates an output signal to a node 2. The signal line driving circuit 25 functions as an inverter comprising an NMOS transistor QN10 and a PMOS transistor QP10. The signal line driving circuit 25 buffers a signal supplied from the node 2 and supplies the signal to an output signal line 10.
A positive potential VCC of a positive power supply VCC and a ground potential GND of a negative power supply GND are applied to each of the logic circuit 20 and the signal line driving circuit 25. The positive power supply VCC is an external power supply or an internal lower power supply. The output signal line 10 has a line capacitance CL. In the description of the present invention, for sake of simplicity, an explanation is made on the assumption that an input signal is supplied to each circuit block through one signal line, i.e., the input signal line 1 and an output signal is generated from the block through one signal line, i.e., the output signal line 10. In some cases, signals are supplied to each circuit block through a plurality of signal lines and are generated from the block through a plurality of signal lines. Generally, a logic threshold level of the logic circuit is set to the midpoint of the levels VCC and GND, i.e., ½×VCC.
Operating current in the circuit block according to the first related art of FIG. 10 is consumed by charging and discharging the capacitance at each node in the circuit block and the line capacitance CL. The potential of each node and that of the output signal line 10 swing between VCC and GND. When VCC is set to low voltage, therefore, the voltage swing in each node and the signal line is lowered, thus reducing the operating current. Disadvantageously, however, the low voltage VCC leads to a reduction in working speed of the circuit block. According to one of approaches for overcoming the disadvantage, a threshold voltage (VT) of each of NMOS and PMOS transistors of each circuit block is reduced, so that the reduction in working speed can be prevented. Unfortunately, when the threshold voltage of each transistor is reduced, OFF-state leakage current increases. This leads to an increase in standby current.
As patterns of semiconductor circuit devices are designed finer, the size of each circuit block tends to be smaller. On the other hand, the length of each signal line arranged between circuit blocks tends to be longer with increasing scale integration. Regarding the operating current in the circuit block of FIG. 10, therefore, the ratio of current consumed by charging and discharging the capacitance of each node in the circuit block becomes lower. Accordingly, current consumed by charging and discharging the line capacitance CL of the output signal line 10 accounts for most of the operating current. For this reason, a low-voltage-swing signal line driving method is proposed as disclosed in Japanese Unexamined Patent Publications (JP-A) Nos. 2-7466 and 7-307661. According to the method, only an output signal line is driven by a low voltage amplitude to reduce operating current and a circuit block is driven at high voltage to keep high working speed.
FIG. 11 shows a low-voltage-swing signal line driving circuit shown in FIG. 13 of Japanese Unexamined Patent Application Publication No. 7-307661 as a second related art. As distinct from the signal line driving circuit 25 in FIG. 10, in a signal line driving circuit 26, the source node of a PMOS transistor QP11 is connected to an internal power supply VL. The potential of the internal power supply VL is lower than the level VCC. A high logic level of an output signal line 11 is VL. Accordingly, the range of voltage swing of a signal line is up to the level VL that is low. Thus, operating current consumed by charging and discharging the line capacitance CL can be reduced. Similar to the circuit block in FIG. 10, the potential VCC is applied to the logic circuit 20. Therefore, a reduction in operation speed does not occur in the logic circuit 20.
According to the above-mentioned technique of driving only an output signal line with low-voltage-swing, as shown in a third related art in FIG. 12, a level converting circuit is added to an input portion of a circuit block. A low logic level of the input signal line 1 is GND and a high logic level thereof is VL. Since the level converting circuit is arranged, the range of the logic level of the input signal line 1 is increased between GND and VCC and, after that, a signal is input to the logic circuit 20. Generally, a logic threshold of the level converting circuit is set to the midpoint of the voltage swing of the corresponding signal line, i.e., ½×VL.
According to the second related art related to the low-voltage-swing signal line driving method of FIG. 11, disadvantageously, when the output signal line 11 changes from a low level to a high level, driving speed remarkably becomes slow. FIG. 13 is a timing chart showing the operations of the circuit blocks in FIGS. 10 and 11. The output-signal lines 10 and 11 represent the operations of the output signal lines of FIGS. 10 and 11, respectively. When the node 2 changes from the high level to the low level at time T1, the output signal lines 10 and 11 change from the level GND to the levels VCC and VL which are high logic levels, respectively. Time TA represents timing at which the voltage of the output signal line 10 reaches a logic threshold of a circuit which receives a signal from the output signal line 10, i.e., ½×VCC. Time TB indicates timing at which the voltage of the output signal line 11 reaches a logic threshold of a circuit which receives a signal from the output signal line 11, i.e., ½×VL. Therefore, the difference (TA−T1) and that (TB−T1) represent signal transfer delays. Time TB is delayed longer than time TA. This means a reduction in operating speed of the semiconductor circuit device.
The reason is as follows. In the circuit block of FIG. 10, the source node of the PMOS transistor QP10 is connected to the power supply VCC. When the PMOS transistor QP10 turns on, therefore, the gate of the PMOS transistor QP10 is in the level GND and the difference in potential (VGS) between the gate and the source thereof is in the level VCC. On the other hand, in the circuit block of FIG. 11, the potential difference VGS of the PMOS transistor QP11 is in the level VL that is low. Consequently, the ON-state current of the PMOS transistor QP11 is low. It takes much time to charge the line capacitance CL of the output signal line 11.
On the other hand, when the node 2 changes from the low level to the high level at time T2, the output signal lines 10 and 11 change from the levels VCC and VL to the level GND, respectively. At that time, in both of the circuit blocks of FIGS. 10 and 11, the potential difference VGS of each of the NMOS transistor QN10 and an NMOS transistor QN11 becomes the level VCC. The ON-state current of the NMOS transistor QN10 is equivalent to that of the NMOS transistor QN11. As shown at time TC, signal transfer speed in FIG. 10 is substantially the same as that in FIG. 11.
FIG. 14 shows a circuit according to a fourth related art. According to the fourth related art, when the output signal line 13 goes from the low logic level to the high logic level, a potential difference VGS of the PMOS transistor QP12 is increased to reduce a delay in signal transfer speed. FIG. 15 is a timing chart showing the operation in the circuit block of FIG. 14.
The circuit block in FIG. 14 will now be described. The structure of the logic circuit 20 is the same as that in FIG. 11. A signal line driving circuit 28 includes an NMOS transistor QN12, a PMOS transistor QP12, a delay circuit DELAY1, a PMOS transistor QP13, an inverter circuit INV2, and a PMOS transistor QP14. The gate of the NMOS transistor QN12 is connected to the node 2, the source is connected to the ground GND, and the drain is connected to an output signal line 13. The gate of the PMOS transistor QP12 is connected to the node 2, the source is connected to a node 15, and the drain is connected to the output signal line 13. The delay circuit DELAY1 receives an input from the node 2 and generates an output to a node 2D. The gate of the PMOS transistor QP13 is connected to the node 2D, the source is connected to the internal power supply VL, and the drain is connected to the node 15. An inverter circuit INV2 receives an input from the node 2D and generates an output to a node 14. The gate of the PMOS transistor QP14 is connected to the node 14, the source is connected to the power supply VCC, and the drain is connected to the node 15. The potential VCC is applied from a power supply (not shown) to each of the delay circuit DELAY1 and the inverter circuit INV2. Accordingly, a high logic level at each of the node 2D and the node 14 is VCC.
The operation of this circuit will now be described with reference to FIG. 15. The node 2 is in the high level for a period before T1. For this period, the node 2D is in the high level and the node 14 is in the low level. Consequently, the PMOS transistor QP13 is in the OFF state, the PMOS transistor QP14 is in the ON state, and the node 15 is in the level VCC.
At time T1, the node 2 goes from the high logic level to the low logic level. At time T1D that is delayed from time T1 by the amount of delay time of the delay circuit DELAY1, the node 2D goes from the high level to the low level and the node 14 changes from the low level to the high level. For a period from T1 to T1D, since the PMOS transistor QP13 is in the OFF state and the PMOS transistor QP14 is in the ON state, the potential VCC is applied to the node 15. In addition, the NMOS transistor QN12 turns off and the PMOS transistor QP12 turns on. The potential difference VGS of the PMOS transistor QP12 goes to substantially the level VCC. Thus, the PMOS transistor QP12 has high ON-state current. Consequently, the output signal line 13 rapidly changes from the level GND to the high logic level.
After time T1D, since the PMOS transistor QP13 turns on and the PMOS transistor QP14 turns off, the potential VL is applied to the node 15, so that the output signal line 13 goes to the level VL. Time T1D, i.e., the delay time of the delay circuit DELAY1 is set to time elapsed until the output signal line 13 goes to the level VL.
At time T2, the node 2 changes from the low logic level to the high logic level. At that time, the NMOS transistor QN12 turns on and the PMOS transistor QP12 turns off. Since the potential difference VGS of the NMOS transistor QN12 goes to the level VCC, the NMOS transistor QN12 has high ON-state current, so that the output signal line 13 rapidly changes from the level VL to the level GND.
At time T2D that is delayed from time T2 by the delay time of the delay circuit DELAY1, the node 2D changes from the low level to the high level and the node 14 goes from the high level to the low level. Consequently, the PMOS transistor QP13 turns off and the PMOS transistor QP14 turns on, so that the node 15 goes to the level VCC.
As mentioned above, when the circuit block in FIG. 14 is used, the output signal line can be changed from the level GND to the level VL at higher speed than that of the circuit block in FIG. 11. However, there are the following disadvantages.
First, it is necessary to set the potential difference VGS of the PMOS transistor QP12 to a large value so that the signal line rapidly changes from the level GND to the high logic level for a period from T1 to T1D. Therefore, the node 15 has to be held in a high level close to the level VCC. For this purpose, the capacity of the ON-state current of the PMOS transistor QP14 has to be higher than that of the PMOS transistor QP12. This means that the size of the PMOS transistor QP14 is larger than that of the PMOS transistor QP12. This leads to high operating current in charging and discharging the gate capacitance of the PMOS transistor QP14. Although the low-voltage-swing on the signal line is originally achieved to reduce operating current, disadvantageously, the effect of the low-voltage-swing is reduced.
Second, it is difficult to set the delay time of the delay circuit DELAY1. Particularly, due to a variation in transistor process or a change in temperature, the delay time of the delay circuit DELAY1 and the ON-state current of the PMOS transistor QP12 vary. In the case where the signal line changes from the level GND to the high logic level, it is impossible to precisely set the delay time of the delay circuit DELAY1 on any variable condition at timing when the signal line goes to the level VL. Depending on a variation in transistor process or a change in temperature, an error may be included in the level VL for the signal line.
Third, if the error occurs in the signal line level VL at time T1D, it is necessary to set the output signal line 13 to the level VL as soon as possible after time T1D. For this purpose, the size of the PMOS transistor QP13 has to be increased. This leads to an increase in gate capacitance of the PMOS transistor QP-13. Disadvantageously, the operating current is increased to charge and discharge the increased gate capacitance.